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| CXG1092N SP5T GSM Triple-Band Antenna Switch For the availability of this product, please contact the sales office. Description The CXG1092N is a high power antenna MMIC switch for use in triple-band GSM handsets. One antenna can be routed to either of the 2 Tx or 3 Rx ports. Features * 4 CMOS compatible control lines * Standby control * 34.5dBm power handling at 5.0V (GSM900) * Low second harmonic < -36dBm at 34.5dBm * Small package size: 20-pin SSOP (6.4 x 5.0 x 1.25mm) Applications Triple-band handsets using combinations of GSM900/DCS1800/PCS1900 and DECT Structure GaAs J-FET MMIC (The Sony JFET process is used for low insertion loss.) 20 pin SSOP (Plastic) Absolute Maximum Ratings (Ta = 25C) * Bias voltage VDD 7 * Control voltage * Operating temperature * Storage temperature Vctl Topr Tstg V 5 V -35 to +85 C -65 to +150 C Note on Handling GaAs MMICs are ESD sensitive devices. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E99Z07-PS CXG1092N Truth Table On Pass Ant.-Tx1 GSM900 Ant.-Tx2 GSM1800 Ant.-Rx1 GSM900/1800/1900 Ant.-Rx2 GSM900/1800/1900 Ant.-Rx3 GSM900/1800/1900 OFF GSM900 H L H L L -- DCS1800 L H L H L -- PCS1900 L L L L H -- Rx ON L L H H H -- STDBY H H H H H L CMOS logic values Logic High Low Min. 2.4 0.0 Typ. 2.8 Max. 3.2 0.4 (Ta = 25C) Unit V V -2- CXG1092N Electrical Characteristics Item Symbol Port Ant-Tx1, Tx2 1 2 Insertion loss IL Ant-Rx1, Rx2, Rx3 3 4 5 Ant-Tx1, Tx2 Isolation ISO. 3 4, 5 Ant-Rx1, Rx2, Rx3 1 2 VSWR HarmonicsNote) P1dB compression input power Control current Supply current Tx mode Supply current Rx mode Leakage current VSWR 2fo 3fo P1dB Ictl ITX IRX IIK STBY = H TxON = L STBY = H RxON = H STBY = L 1, 2 Ant-Tx1, Tx2 Ant-Tx1 Ant-Tx2 1, 2 36 35.5 15 14 18 17 1.2 Condition Min. Typ. 0.6 0.7 0.6 0.85 0.9 (Ta = 25C) Max. 0.9 1.0 0.9 1.1 1.15 Unit dB dB dB dB dB dB dB dB dB -36 -30 dBm dBm dBm 170 1 1 100 A mA mA A 1 Pin 1 = 34.5dBm, 880 to 915MHz, VDD = 5.0V (GSM Tx) 2 Pin 2 = 32dBm, 1710 to 1910MHz, VDD = 5.0V (DCS & PCS Tx) 3 Pin 3 = 10dBm, 925 to 960MHz (GSM Rx) 4 Pin 4 = 10dBm, 1805 to 1880MHz (DCS Rx) 5 Pin 5 = 10dBm, 1930 to 1990MHz (PCS Rx) Note) Harmonics measured with Tx inputs harmonically matched. Sony recommends the use of harmonic matching to ensure optimum device performance Application Note (1). -3- CXG1092N Recommended Circuit (RRF) 11 ANT 12 GND 13 GND 14 VDD 15 GND 16 GSM900 CTL 17 DCS1800 CTL 18 PCS1900 CTL 19 RX ON 20 GND Tx1 10 GND Tx2 GND Rx1 GND Rx2 GND Rx3 STDBY 9 8 (RRF) (1) (RRF) 7 6 5 4 3 2 1 Recommended PCB Layout As indicated in the diagram AC coupling capacitors are necessary to the Ant, Tx1, Tx2, Rx1, Rx2 and Rx3 pins, and decoupling capacitors are necessary to the VDD, STDBY and CTL lines. The ground plane should be included under the device and all ground pins connected to this. RRF (200k) is used to stabilize the electrical characteristics at the high power signal input. These resistors are required to ensure correct operation of the switch. 1 See Application Note (1). -4- CXG1092N Application Note (1) Impedance matching for harmonic minimization To achieve the 2nd harmonic levels lower than -36dBm for GSM900 Design of 1.8GHz harmonic matching network and the 900MHz trap network is dependent on the board design and components. 1800MHz Matching Network ANT 11 GND 12 GND 13 VDD 14 GND 15 GSM900 CTL 16 DCS1800 CTL 17 PCS1900 CTL 18 RX ON 19 GND 20 10 9 8 7 6 5 4 3 2 1 Tx1 GND Tx2 GND Rx1 GND Rx2 GND Rx3 STDBY 900MHz Trap LPF Application Note (2) Operating the CXG1092 from a 3V supply Technique Logic lines 200k 200k Tx1 Tx2 Rx1 CXG1092N Rx2 Rx3 C VDD Additional Components C: 0603 CAPS, few F R: 200R D: Low Turn-on voltage diode VDD @2.7V 577s R D 4.0V D.C. Out C ANT Allows use of the CXG1092N (SP5T) in handsets with 3V min. battery voltage (2.7V SW supply). The CXG1092N is for 5V nominal battery voltage but work well down to 4V. Fundamentally, the 577s time slot waveform is used to increase the 2.7V supply to over 4V. This waveform may be taken from the PA ramping input (or drain supply in case of drain power control) or via the TX ON/OFF logic. 200k -5- CXG1092N Package Outline Unit: mm 20PIN SSOP(PLASTIC) 5.0 0.05 1.25MAX S 11 0.1 A 20 4.4 0.05 6.4 0.2 A 1 10 0.5 0.1 S 0.1 b 0.1 M S A B 0.17 0.03 b = 0.22 0.05 0.1 0.1 b = 0.2 0.03 0.6 0.15 (0.2) (0.15) 0.25 0 to 10 DETAIL A (0.5) DETAIL B : SOLDER DETAIL B : PALLADIUM NOTE: Dimension "" does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SSOP-20P-L03 SSOP020-P-0044 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING COPPER ALLOY 0.1g -6- + 0.03 0.15 - 0.01 Sony Corporation |
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